`timescale 1ns / 1ps

module rnd_generator_register(
	input [31:0] rnd_seed,
	output [14:0] rnd_num0,
	output [14:0] rnd_num1,
	output [14:0] rnd_num2,
	output [14:0] rnd_num3,
	output [14:0] rnd_num4
	);
	
	reg [31:0] recv_seed;
	reg [3:0] i;
	
	reg [14:0] rnd_num [4:0];
	assign rnd_num0 = rnd_num[0];
	assign rnd_num1 = rnd_num[1];
	assign rnd_num2 = rnd_num[2];
	assign rnd_num3 = rnd_num[3];
	assign rnd_num4 = rnd_num[4];
	
	always @(rnd_seed) begin
		if (rnd_seed % 2 == 0) begin
			recv_seed = rnd_seed + 1;
		end else begin
			recv_seed = rnd_seed;
		end
		
		for (i=0 ; i<=4 ; i=i+1) begin
			rnd_num[i] = recv_seed[15:1];
			recv_seed = recv_seed * recv_seed;
		end
	end
endmodule

